A New Design Reuse Approach for VOIP Implementation Into FPSOCS and ASICS


  • Nouma Izeboudjen Development Centre of Advanced Technologies (CDTA), Microelectronic and Nanotechnology Division
  • Mohammed Bakiri




Voice over IP, Systems on Chip, FPGA, Design reuse


The aim of this paper is to present a new design reuse approach for automatic generation of Voice over Internet Protocol (VOIP) hardware description and implementation into FPSOCs and ASICs. Our motivation behind this work is justified by the following arguments: first, VOIP-based System on chip (SOC) implementation is an emerging research and development area, where innovative applications can be implemented. Second, these systems are very complex and due to time to market pressure, there is a need to build platforms that help the designer explore different architectural possibilities and choose the circuit that best corresponds to the specifications. Third, we aim to develop hardware, design, methods, and tools that are used in software like the MATLAB tool for VOIP implementation. To achieve our goal, the proposed design approach is based on a modular design of the VOIP architecture. The originality of our approach is the application of the design for reuse (DFR) and the design with reuse (DWR) concepts. To validate the approach, a case study of a SOC based on the OR1K processor is studied. We demonstrate that the proposed SoC architecture is reconfigurable, scalable and the final RTL code can be reused for any FPSOC or ASIC technology. As an example, Performances measures, in the VIRTEX-5 FPGA device family, and ASIC 65nm technology are shown in this paper


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How to Cite

Izeboudjen, N. ., & Bakiri, M. (2021). A New Design Reuse Approach for VOIP Implementation Into FPSOCS and ASICS. Scholars Journal of Science and Technology, 2(3), 319–327. https://doi.org/10.53075/Ijmsirq/1277686759756876